package uart

import chisel3._
import chisel3.util._

import uart._

class UART_top extends Module{
    val io = IO(new Bundle{
        val uart_rxd    = Input(Bool())
        val uart_txd    = Output(Bool())
        val led         = Output(UInt(8.W))
    })

    val rx_done     =   Wire(Bool())
    val rx_data     =   Wire(UInt(8.W))

    val tx_busy     =   Wire(Bool())
    val tx_done     =   Wire(Bool())

    val M_uart_rx   =   Module(new UART_rx)
    val M_uart_tx   =   Module(new UART_tx)

    io.led          :=  rx_data             

    M_uart_rx.io.i_serial_data  :=  io.uart_rxd
    rx_done                     :=  M_uart_rx.io.o_rx_done
    rx_data                     :=  M_uart_rx.io.o_data

    M_uart_tx.io.i_tx_trig      :=  rx_done
    M_uart_tx.io.i_data         :=  rx_data
    tx_busy                     :=  M_uart_tx.io.o_tx_busy
    tx_done                     :=  M_uart_tx.io.o_tx_done
    io.uart_txd                 :=  M_uart_tx.io.o_serial_data
}